Data converter

ABSTRACT

A data converter comprises a discrete-time sigma delta modulator e.g. for driving a Class-D power amplifier. The low-pass filter of the sigma delta modulator is modified by adding a suitably positioned pole to lower the oscillation frequency (limit cycle) of the sigma delta modulator in order to obtain increased clustering of the pulses applied to the output of the data converter.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a 371 of PCT/IB03/04220 filed on Sep. 22, 2003.

FIELD OF INVENTION AND RELATED ART

The invention relates to a data converter comprising a sigma deltamodulator intended to operate at a specific sample frequency, said sigmadelta modulator comprising in a feedback loop a comparator, adiscrete-time low-pass filter and a quantizer in that order, in whichthe comparator is arranged to compare the output of the quantizer withthe input signal to be converted. Such data converter is known from thearticle “Digital Power Amplification Using Sigma-Delta Modulation andBit Flipping” by A. J. Margrath and M. B. Sandler in J. AudioEngineering Society, Vol. 45, No 6, pp 476–487, June 1997.

The invention is particularly but not exclusively of interest to drivingswitching power amplifiers (class D amplifiers). These amplifiers areused for instance in motor drivers, supply regulators and audioamplifiers. Conventional class D amplifiers use analog pulse widthmodulators. However, there is a need for digital pulse width modulatorssince nowadays signals are often available and processed in the digitaldomain. But the problem is, that digital pulse width modulators in whicha direct translation of signal amplitudes into pulses with proportionalwidth takes place, suffer from considerable signal distortionoriginating from the sampler. It is possible to reduce this distortionby using very high sample frequencies, however this has the drawbackthat quite complex and expensive circuits are required.

The approach followed in the above-mentioned article is to translate thedigital PCM input signals into a pulse density modulated signal by meansof a sigma delta modulator. Subsequently, the output pulses of the sigmadelta modulator are used to switch the power amplifier, which operatesas a 1-bit D/A converter, and the output of the power amplifier isapplied to low-pass filtering means constituted wholly or partly by theload of the power amplifier. However, the problem with conventionalsigma delta modulators is that the pulse density modulated signal hasmuch higher switching frequencies than pulse width modulated signals.This limits their usability, especially in power converters, because thepower losses in class D amplifiers increase proportional with the numberof switching flanks. In the aforementioned article a method is proposedthat uses a separate controller around the sigma delta modulator toforce the sigma delta modulator to generate low frequency pulsepatterns. This method is called “bit flipping” and it leads to quitepromising results, but with the drawback of increased circuitcomplexity.

The present invention has for an object to force the sigma deltamodulator to generate low-frequency pulse patterns with much lowercircuit complexity than the solution of the said article, while there isa large flexibility in the choice of the average length of these pulsepatterns and the data converter according to the present invention istherefore characterized in that, for decreasing the idle oscillationfrequency of the sigma delta modulator, the discrete-time low-passfilter is arranged to have a 180° phase delay with positive group delayat a frequency that is at least four times lower than the samplefrequency (f_(s)). The group delay is normally defined as the negativeof the slope of the phase versus frequency characteristic. Thereforethis means that according to the invention the phase versus frequencycharacteristic passes with increasing frequency downwardly through a180° level at a frequency that is at least four times lower than thesample frequency (fs).

Theoretically, each sigma delta modulator generates an oscillationpattern, often called “limit cycle”. An analog sigma delta modulatorwith a single integrator followed by a comparator would in theory startto oscillate at an infinite frequency and the average output signalwould be equal to the input signal. An equivalent digital sigma deltamodulator with zero input signal would start to oscillate around halfthe sample frequency because of the inherent time delay of thediscrete-time integrator. The idea behind the present invention is that,by properly dimensioning the discrete-time low-pass filter, the sigmadelta modulator may be forced to oscillate at a frequency which issubstantially lower than is the case with prior art sigma deltamodulators without “bit flipping” and that this reduction in oscillatorfrequency leads to broader pulse patterns and correspondingly lesserswitching flanks in the output of the sigma delta modulator.

For instance, in a sigma delta modulator for audio signals with astandard CD-audio sample rate of 44.1 KHz which is firstly upsampled toa sample rate f_(s) of 256×44.1 KHz, the average oscillation frequencymay be reduced from f_(s)/2=128×44.1 KHz to about 8×44.1 KHz, i.e. by afactor 16. The embodiment to be described afterwards in this applicationis based on these frequency-figures.

The most important advantage of a data converter according to thepresent invention is the much lower switching frequency with thecorresponding reduction in energy dissipation, especially when theconverter is used to drive a class D power amplifier. Moreover, thelower switching frequency makes the data converter of the presentinvention less sensitive to the most important problems associated with1-bit converters, namely Inter Symbol Interference (ISI) and clockjitter. The average width of the pulses is much larger than for priorart 1-bit converters, thus the relative variance of the pulse-widths dueto differences in the switching moments is smaller. Furthermore theswitching frequency of the proposed data converter is more stable i.e.less dependent of the input signal, than the switching frequency ofconventional data converters. Therefore the analog back-end behind thedata converter of the present invention will generate less harmonicdistortion. With the present invention most switching inaccuracies willlead to an increase of the noise floor and much less to an increase ofthe harmonic distortion.

SUMMARY OF THE INVENTION

A preferred embodiment of the data converter according to the presentinvention is characterized in that the transfer function of thediscrete-time low-pass filter comprises, in its complex z-plane, aplurality of poles at or close to the point (1;0) of the unit circle ofsaid plane and an additional pole on the positive real axis of saidplane at a value between 0.20 and 0.92 for decreasing the idleoscillation frequency of the sigma delta modulator. Said plurality ofpoles may be positioned in known manner so that a suitable low frequencypass band, e.g. with Butterworth or Chebyshev characteristic, and asufficiently steep roll off is obtained. These poles operate mainly inthe baseband of the signals to be converted and substantially contributeto the noise shaping, i.e. the reduction of the noise power in saidbaseband. The additional pole on the real axis is mainly operative inthe higher frequency band and determines the average frequency at whichthe loop will oscillate i.e. the average length of the pulse patterns.In the example given below this pole is positioned at the point (0.88;0)of the complex z-plane. Positioning the additional pole further awayfrom the point (1;0) would increase the oscillator frequency, i.e. themore the additional pole is away from the point (1;0) the less influencethe pole has on the pulse pattern. If it is desired to further decreasethe oscillator frequency the pole has to be positioned closer to thepoint (1;0), however any further shift beyond approximately 0.92 wouldbring the pole too close to the point (1;0) and would cause the pole tolose any control over the oscillation pattern.

Preferably the DA-converter of the present invention is furthercharacterized in that the transfer function of the discrete-timelow-pass filter has a number of poles that exceeds the number of zeroesof said discrete-time low-pass filter by at least 2. Because usually ina digital sigma delta modulator the number of poles exceeds the numberof zeroes by one, this means that the additional pole is introducedwithout the introduction of an additional zero. The position of thezeroes is a compromise between the stability requirements and the noiseshaping requirements of the sigma delta modulator and this compromise isbest preserved when the higher order characteristic at the lowerfrequencies is followed by a first order characteristic at theintermediate frequencies. By adding the additional pole withoutintroducing an additional zero, a second order characteristic in thefrequency range above said intermediate frequencies is obtained whilethe first order characteristic for the intermediate frequencies ispreserved. However, in some cases, it is possible to place an additionalzero somewhere on the real axis to change the phase characteristic ofthe filter and thereby the oscillation frequency, without a significantalteration of the noise shaping characteristics.

A suitable data converter according to the invention may becharacterized in that the discrete-time low-pass filter comprises acascade of integrators, summing means to sum the output of saidintegrators through coefficient multipliers to constitute the output ofthe discrete-time low-pass filter and a single order low-pass filtersection arranged in series with the first of the integrators of saidcascade for producing said additional pole on the real axis of thecomplex z-plane. The low-pass filter section may be placed either beforeor after the first of the integrators but, if the addition of a zeroshould be avoided, before the first tap to the summing means. It has tobe remarked that alternatively the low-pass filter section may be placedin the output of the summing means. It may also be remarked that,without departing from the scope of the invention, some or all of thezeros may be made by feeding back the output of the quantizer to one ormore points in the discrete-time low-pass filter.

It may further be observed that the data converter of the presentinvention is not restricted to converting digital PCM data to single-bitdigital data, but may also be arranged to convert analog data tosingle-bit digital data. Such converter may e.g. comprise a single-bitD/A converter to convert the output of the quantizer to analog pulsesfor application to the (analog) comparator and a sampler to sample theanalog output of the comparator and to supply the analog samples soobtained to the discrete-time low-pass filter.

BRIEF DESCRIPTION OF THE DRAWING

The invention will now be described with reference to the accompanyingdrawings. Herein:

FIG. 1 shows a schematic diagram of an embodiment of a data converteraccording to the present invention,

FIG. 2 shows amplitude versus frequency diagrams of the transferfunction of the digital low-pass filter used in the embodiment of FIG.2. and

FIG. 3 shows phase versus frequency diagrams of the transfer function ofthe digital low-pass filter used in the embodiment of FIG. 2.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The data converter of FIG. 1 comprises a digital low-pass filter FD thatreceives at its input terminal a digital input signal U, e.g. a digitalPCM-signal, through a comparator G that might be a simple subtracter.The output signal V of the digital low-pass filter is quantized in aone-bit quantizer Q and the output W of the quantizer is fed back to thecomparator G. Therefore, the comparator subtracts the quantizer output Wfrom the input signal U, the difference signal U-W is passed to thedigital low-pass filter FD and the low-frequency content of thisdifference signal U-W is applied to the quantizer. The output of thequantizer is a series of single-bit pulses, which may, with respect to areference value, have either +1 or −1 value. The structure of comparatorG, digital low-pass filter FD and quantizer Q constitutes adiscrete-time sigma delta modulator which keeps the difference betweenthe value of the PCM input signal and the low frequency content of thepulses W as small as possible. Therefore, when the input signal valueincreases, the number of +1 pulses in the output of the quantizerincreases and the number of −1 pulses decreases. Equally, when the valueof the input signal decreases, the number of +1 pulses in thequantizer-output decreases and the number of −1 pulses increases. Wherethe digital input signal U of the sigma delta modulator comprises bitswhose value is dependent on the position of the bits, i.e. moresignificant bits and less significant bits, the digital output pulses Wall have the same significance. In contrast to the digital input signal,the digital output signal of the sigma delta modulator has alow-frequency content which substantially matches the analog signalcontent and this analog signal content can therefore be recovered by asuitable single bit DA converter followed by an analog low-pass filter.In practice the single-bit DA converter may contain a switched poweramplifier (class-D amplifier) and the analog low-pass filter maycomprise one or more loudspeakers.

The total power of the output signal W of the sigma delta modulator issubstantially higher than the power of the baseband signal, which meansthat a certain frequency band outside the signal band has to be used todistribute the remaining output power (the noise power). In order tosufficiently shape this noise power to the remaining frequency band, thedigital low-pass filter of the sigma delta modulator has to be ofsufficiently high order. In the arrangement of FIG. 1 the digitallow-pass filter FD comprises six integrators I₁ to I₆ in cascade. Eachof the integrators has a z-transfer 1/(z−1). The integrators I₁ and I₂each constitute a pole in point (1;0) on the unit circle of the complexz-plane. The integrators I₃ and I₄ would also constitute two poles inpoint (1;0) however the output of the integrator I₄ is, through amultiplier A₁, subtracted from the input of integrator I₃ by means of asubtracter S₁ and this measure causes an upward shift of one of the twopoles and a downward shift of the other of the two poles to obtainconjugate poles in the points (1; ±sqrt(A₁)). In the same way theintegrators I₅ and I₆ have a multiplier A₂ and a subtracter S₂ in theinput lead to the integrator I₅ in order to create two conjugate polesin the points (1; ±sqrt(A₂)).

The outputs of the six integrators I₁ to I₆ are each connected to acoefficient-multiplier C₁ to C₆ respectively and the outputs of thesecoefficient-multipliers are summed in a summer AD to constitute theoutput V of the digital low-pass filter FD. As is well known, thisstructure creates a number of zeros in the transfer function of thedigital low-pass filter. The six coefficient-multipliers of FIG. 1create five zeros whose positions in the complex z-plane may be chosenby proper choice of the coefficients C₁ to C₆. The six poles lie on orvery close to the point (1;0) of the complex z-plane and are distributedsuch that they guarantee a sufficient signal-to-noise ratio over theentire pass band and a sufficiently steep edge in the transfercharacteristic above the pass band. The five zeros are located to obtainoptimal stability at high input signal values and optimal shaping of thesample noise in the higher frequency band.

The arrangement of FIG. 1 further comprises a low-pass filter section Lpositioned between the input terminal of the digital low-pass filter FDand the integrator I₁. The low-pass filter section L has a transferfunction 1/(z−B) and may e.g. be implemented by an adder followed by asample delay, with the output of the delay being fed back to the adder,through a multiplier having factor B. An integrator whose output ismultiplied by 1−B and then subtracted from its input may also implementit. The low-pass filter section L generates an additional pole on thehorizontal axis of the complex z-plane at position (B;0). The section Lmay also be positioned behind the integrator I₁, but preferably beforethe tap to coefficient-multiplier C₁, so that the section L does notcreate an additional zero. With the section L the low-pass filter FD isof 7^(th) order with seven poles and five zeros. The position of thepoles and zeros of an arrangement tested in practice is listed in thefollowing table:

Real part Imaginary part Pole 1 1 0 Pole 2 1 0 Pole 3 1 0.0107 Pole 4 1−0.0107 Pole 5 1 0.0075 Pole 6 1 −0.0075 Pole 7 0.88 0 Zero 1 0.99330.0198 Zero 2 0.9933 −0.0198 Zero 3 0.9836 0.0121 Zero 4 0.9836 −0.0121Zero 5 0.9805 0

The integrators I₃, I₄ and the multiplier A₁ with coefficientA1=0.00011449 create the two conjugate poles 3 and 4. Equally theintegrators I₅, I₆ and the multiplier A₂ with coefficient A2=0.00005625create the two conjugate poles 5 and 6. Poles 1 and 2 are created by theintegrators I₁ and I₂ respectively and pole 7 is created by the low-passfilter section L with B=0.88. It may be observed that the poles 1 to 6are all located at or in the neighborhood of the point (1;0) of thecomplex z-plane. This means that these six poles have their maininfluence on the frequencies below 0.01*f_(s)/2 i.e. the frequencies ofand close to the audio base band. In contradistinction herewith theadditional pole 7 is located substantially more remote from the point(1;0) and therefore its influence is mainly on the frequencies from0.01*f_(s)/2 to 1*f_(s)/2. With f_(s)=256*44.1 KHz the six poles aremainly operative below 56;5 KHz while the pole 7 is mainly operative inthe frequency region between 56.5 KHz and 5650 KHz. The five zeros arepreferably located as far as possible remote from the point (1;0) inorder to improve the noise shaping, however this is limited by thestability requirements. In the example given above the zeroes arelocated, so that the turnover point between the higher (sixth) ordertransfer and the lower (first) order transfer is at about 80 KHz.

From the locations of the poles 2 to 6 and the zeros 1 to 5 given abovethe coefficients C₁ to C₆ may be calculated. This can be done by firstcalculating the coefficients C₅ and C₆ at the locations of the poles 5and 6, then calculating the coefficients C₃ and C₄ at the locations ofthe poles 3 and 4 with the calculated coefficients C₅ and C₆ and finallycalculating the coefficient C₂ at the location of the pole 2 with thecalculated coefficients C₃ to C₆. The result with the pole and zerolocations given above is as follows:

C₁ C₂ C₃ C₄ C₅ C₆ 1 0.0657 0.00202198 3.38701E−5 4.49308E−7 1.2107E−9

In practice the coefficients C₁ to C₆ and the coefficients A₁ and A₂ maypreferably be transformed into versions that are powers of two orsummations of powers of two, in order to reduce circuit complexity.

The function of the additional pole 7 may best be explained as follows.The sigma delta modulator feed back loop will always oscillate. Assumethat the digital input signal U is zero during a large number of sampleperiods. Then, without the pole 7, the quantizer Q will output asequence of alternating +1 and −1 pulses. In other words: the looposcillates at a frequency f_(s)/2=5650 KHz. At other input signal levelsthe oscillating frequency will change in order to generate differentpulse patterns such as e.g. +1, +1, −1, +1, +1, −1 etc. or +1, +1, +1,−1, −1, +1, +1, −1, −1. The function of the additional pole 7 is tolower the oscillation frequency i.e. to force the sigma delta modulatorto generate longer pulse patterns. For instance the idle frequency, i.e.the oscillation frequency when the input signal value is zero, may bedecreased to about 8*f_(s)=352.8 KHz; this is a factor 16 lower than theoriginal idle frequency. The pulse pattern at zero input signal value isthen sixteen +1 pulses, sixteen −1 pulses, sixteen +1 pulses etc. and,because these pulses are NRZ, this means that the power amplifier drivenby the data converter has to switch about sixteen 16 times less thanwithout the additional pole 7. The effect of pole 7 may also beillustrated with the graphs of FIGS. 2 and 3 which show theamplitude-versus-frequency and the phase-versus-frequencycharacteristics of the transfer function of the digital low-pass filterFD with and without the pole 7 in the region between 0.01*f_(s)/2 and1*f_(s)/2. The curves I represent these characteristics without thelow-pass section L and the curves II represent these characteristicswith the low-pass filter section L. From the phase-versus-frequencycharacteristics of FIG. 3 it may be seen that the curve I passes the−π(180°) level downwardly at f_(s)/2 while the curve II passes thislevel downwardly at a much lower frequency of about 0.07*f_(s)/2.

It may be noted that the poles and zeros given above are of the digitallow-pass filter FD. More relevant for the oscillatory behavior of thesigma delta modulator are the poles of the closed sigma delta loopitself. However, the quantizer in this loop is highly non-linear, whichmakes such analysis difficult. An approximation of the oscillatorybehavior of the loop may be obtained by considering the quantizer Q as asampling-noise source and an amplifier with signal-dependentamplification factor. Then the poles of the closed loop shift from thepoles of the low-pass filter (with a low amplification factor) either tothe zeros of the low-pass filter or to outside the unit circle of thez-plane (with a high amplification factor). Then the sigma-deltamodulator will oscillate at approximately the frequency correspondingwith the intersection of the trajectory of such shifting pole with theunit circle. Such trajectory, usually called the “root locus”, may beestablished and analyzed with for example the ©MatLab tool.

1. A data converter comprising a sigma delta modulator intended tooperate at a specific sample frequency said sigma delta modulatorcomprising in a feedback loop a comparators, a discrete-time low-passfilter and a quantizer in that order, in which the comparator isarranged to compare the output of the quantizer with the input signal tobe converted, characterized in that, for decreasing the idle oscillationfrequency of the sigma delta modulator, the discrete-time low-passfilter is arranged to have a 180° phase delay with positive group delayat a frequency that is at least four times lower than the samplefrequency.
 2. The data converter as claimed in claim 1 characterized inthat the transfer function of the discrete-time low-pass filtercomprises, in its complex z-plane, a plurality of poles at or close tothe point of the unit circle of said plane and an additional pole on thepositive real axis of said plane at a value between 0.20 and 0.92 fordecreasing the idle oscillation frequency of the sigma delta modulator.3. The data converter as claimed in claim 2 characterized in that thetransfer function of the discrete-time low-pass filter has a number ofpoles that exceeds the number of zeros of said discrete-time low-passfilter by at least
 2. 4. The data converter as claimed in claim 3characterized in that the discrete-time low-pass filter comprises acascade of integrators, summing means to sum the output of saidintegrators through coefficient multipliers to constitute the output ofthe discrete-time low-pass filter and a single order low-pass filtersection positioned in series with the first of the integrators of saidcascade for producing said additional pole on the real axis of thecomplex z-plane.